This invention relates to a semiconductor memory device and particularly to a rewritable semiconductor memory device having a test circuit for a reading speed.
Demand for a rewritable semiconductor membory device which has been developed as a memory device convenient for debugging the program of a microprocessor, is increasing rapidly with the increase in the number of applications of the microprocessors. Most of the presently used rewritable semiconductor memory devices utilize MOS insulated gate type field effect transistors having floating gate electrodes and their degree of integration is 2K bits at minimum and is increasing at a rate of 200% per year. Memory devices having a capacity of 64K are now being used and in the near future a capacity of 256K bits or 1 mega bits will soon be available. As the density of integration increases rapidly, an increase in the time for testing or inspection for judging whether the product is satisfactory or not presents a problem. The test made for checking whether the product is satisfactory or not at the production stage comprises two types. In one type, each memory element is written and a check is made as to whether rewriting is actually possible or not, while in the other type the read out speed is measured. Generally, the read out speed test is made after writing a specific data into a product which has been confirmed that it is rewritable. However, the time necessary for writing takes about 50 milliseconds for one word constituted by 8 bits, so that the time required for judging whether the read out time is satisfactory or not tends to increase with the density of integration thus decreasing productivity. Moreover as the read out speed test is made for specific data, the speed can be observed only when any memory element is in either a "1" or "0" state. In this manner, the content of the observed data obtained by a read out speed test of written specific data is limited and when it is desired to test all memory elements completely, the time of the read out speed test increases. In other words, the observed data is not sufficient despite the fact that the speed test takes a long time. For this reason, where sufficient data for testing all memory elements is to be collected, it would be impossible to cope with the increase in the density of integration.